Semiconductor chip stack structure and method for forming the same

ABSTRACT

Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.

RELATED APPLICATION

This application is a Divisional of U.S. Pat. No. 10/326,775, filed onDec. 20, 2002, now pending, which claims priority from Korean PatentApplication No. 2002-15329, filed on Mar. 21, 2002, which are hereinincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor packaging technologyand, more particularly, to a semiconductor chip stack structure andmethod for forming the same.

2. Description of the Related Art

To provide improved performance, manufacturers of integrated circuit(IC) chips continually strive to increase packaging density, which hasled to the development of, for example, a three-dimensional chip stacktechnology. In this technology, typically, after the wafer is separatedinto individual chips, the chips are stacked before or after they arepackaged.

The three-dimensional stack of the packaged chips, however, increasesthe stack height due to individual package thickness. In contrast, thethree-dimensional stack of the non-packaged (“bare”) chips is relativelythinner, lighter and smaller.

Among the various chip stack structures of the non-packaged chips, astack structure having a pyramid configuration (a relatively smallerupper chip stacked on a lower chip) is known to reduce the stack height.On the other hand, if the upper chip is equal to or larger than thelower chip, a spacer is required between the upper and lower chips forpreventing electrical interference that may occur when a bonding wire onthe lower chip touches a bottom surface of the upper chip. Such aspacer, unfortunately, causes a substantial increase in the stackheight.

FIG. 1 shows a conventional chip stack structure 10. In the chip stack,a semiconductor chip 19 (“a second chip”) is stacked on a lowersemiconductor chip 14 (“a first chip”), using a liquid adhesive 17containing insulating balls 18 as the spacer. The liquid adhesive 17 isapplied on the first chip 14 mounted on a substrate 11. The first chip14 is electrically connected with a wiring pattern 13 of the substrate11 by a bonding wire 16. When the second chip 19 is stacked on the firstchip 14, the bonding wire 16 may touch the second chip 19. Thus,electrical interference between them may occur. The liquid adhesive 17is therefore required so that the second chip 19 may not directlycontact with the bonding wire 16. The liquid adhesive 17 may contain theinsulating balls 18, each having a larger diameter than the highestpoint of the bonding wire 16 from the top surface of the first chip 14.Reference character S1 in FIG. 1 specifies a space between the firstchip 14 and the second chip 19.

The wire bonding between the first chip 14 and the substrate 11 may becarried out by a conventional wire bonding process, such as a ballbonding process on the first chip 14 and subsequently a stitch bondingprocess on the wiring pattern of the substrate 11.

FIG. 2 shows another conventional chip stack structure 20 in which aninsulating adhesive tape 27 serves as a spacer between the first chip 24and the second chip 29. The insulating adhesive tape 27 should bethicker than the highest point of the bonding wire 26 from the topsurface of the first chip 24. Reference character S2 in FIG. 2 specifiesa space between the first chip 24 and the second chip 29.

As described above, the conventional chip stack technology has adisadvantage of increasing the total stack height due to the spacerrequired between the semiconductor chips.

SUMMARY OF THE INVENTION

The present invention is directed to forming a semiconductor chip stackstructure, with which the total height of semiconductor chip stack canbe reduced regardless of the size of a second chip.

A semiconductor chip stack structure comprises a substrate including adie-mounting surface and wiring patterns adjacent the die-mountingsurface. A first semiconductor chip is attached to the die-mountingsurface and includes first electrode pads on a top surface thereof.First conductive bumps are formed on the first electrode pads. Firstbonding wires electrically interconnect the substrate and the firstconductive bumps. The first bonding wires have an expanse substantiallyparallel with the top surface of the first chip. A second semiconductorchip is stacked over the first chip using the expanse. The secondsemiconductor chip includes second electrode pads on a top surfacethereof and is electrically connected to the wiring patterns.

A semiconductor chip stack method in accordance with an embodiment ofthe present invention comprises: (a) providing a substrate including adie-mounting surface and wiring patterns; (b) attaching a first chip tothe die-mounting surface of the substrate; (c) forming first conductivebumps on first electrode pads of the first chip; (d) electricallyinterconnecting the substrate and the first chip through first bondingwires, wherein expanses of the first bonding wires are substantiallyparallel with the top surface of the first chip; (e) stacking a secondchip over the first chip using the expanses; and (f) electricallyinterconnecting second electrode pads of the second chip and the wiringpatterns of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will be readily understood with reference to the followingdetailed description thereof provided in conjunction with theaccompanying drawings, wherein like reference numerals designate likestructural elements, and, in which:

FIGS. 1 and 2 are cross-sectional views of conventional semiconductorchip stack structures.

FIG. 3 is a cross-sectional view of a semiconductor chip stack structurein accordance with an embodiment of the present invention.

FIGS. 4 through 9 are cross-sectional views showing a semiconductor chipstack method in accordance with another embodiment of the presentinvention;

FIG. 4 shows a first semiconductor chip attached to a substrateaccording to an aspect of the present invention;

FIG. 5 shows a first metal bump formed on a first electrode pad of thefirst chip according to another aspect of the present invention;

FIG. 6 shows the first chip and the substrate electrically connected bya reverse wire bonding according to still another aspect of the presentinvention;

FIG. 7 shows an insulating adhesive applied on the first chip accordingto an aspect of the present invention;

FIG. 8 shows a second semiconductor chip on the first chip by theinsulating adhesive according to another aspect of the presentinvention; and

FIG. 9 shows the second chip and the substrate electrically connected bya reverse wire bonding according to still another aspect of the presentinvention.

FIG. 10 is a cross-sectional view of a semiconductor chip stackstructure using a normal wire bonding between the second chip and thesubstrate in accordance with another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Preferred embodiments of the present invention will be described belowwith reference to the accompanying drawings. Like reference numeralsrefer to like elements throughout the drawings.

FIG. 3 is a cross-sectional view of a semiconductor chip stack structurein accordance with one embodiment of the present invention. Referring toFIG. 3, a first semiconductor chip 34 and a second semiconductor chip 40are sequentially stacked on a substrate 31. To minimize a space Sbetween both chips 34 and 40, an insulating adhesive layer 42 is formedon the bottom surface of the second chip 40 and is in contact with afirst bonding wire 38 on the first chip 34.

The substrate 31 may be a conventional printed circuit board. Thesubstrate 31 includes a substrate body 32 having a die-mounting surface32 a, and wiring patterns 33 surrounding the die-mounting surface 32 aon the substrate body 32. Although the preferred embodiment of thepresent invention employs the printed circuit board as the substrate 31,other suitable substrates, such as a lead frame, a tape wiring substrateand a ceramic substrate, which are conventionally used for asemiconductor device, may be used. Further, the wiring pattern 33 may beadditionally formed in and/or under the substrate body 32.

The first chip 34 is attached to the die-mounting surface 32 a of thesubstrate 31 using an adhesive 36. The first chip 34 has first electrodepads 35 formed on the top surface thereof. The first chip 34 is aso-called edge-pad-type or peripheral-pad type chip because the firstelectrode pads 35 are arranged along the periphery of the top surface.Each first electrode pad 35 has a first conductive bump 37 formedthereon.

The first chip 34 is electrically interconnected to the wiring pattern33 of the substrate 31 through the first bonding wire 38. The electricalinterconnection between the first chip 34 and the wiring pattern 33 usesa bump reverse bonding method, which minimizes the height of the firstbonding wire 38 and allows stable stacking of the second chip 40 on thefirst bonding wire 38. Unlike a normal wire bonding, the bump reversebonding is made such that the first bonding wire 38 is ball-bonded tothe wiring pattern 33 corresponding to the first electrode pad 35 of thefirst chip 34 at one end and then stitch-bonded to the first metal bump37 at the other end.

In this embodiment, the second chip 40 has substantially the same sizeas the first chip 34 and is stacked on the first chip 34. The secondchip 40 has the insulating adhesive layer 42 formed on the bottomsurface thereof to prevent the electrical interference between thesecond chip 40 and the first bonding wire 38 of the first chip 34. Aninsulating adhesive 39 is interposed between the first chip 34 and thesecond chip 40. The insulating adhesive 39 provides strong adhesionbetween the first chip 34 and the second chip 40 while protecting theportion of the first bonding wire 38 coupled to the first metal bump 37and the top (active) surface of the first chip 34.

The first bonding wire 38 preferably starts from the wiring pattern 33of the substrate 31 and ends on the first metal bump 37 of the firstchip 34 and has a substantially 90° bend as shown in FIG. 3.Accordingly, the first bonding wire 38 preferably has an expansesubstantially parallel with the top surface of the first chip 34. Thesecond chip 40 having the insulating adhesive layer 42 is preferablyplaced on the expanse of the first bonding wire 38 such that the expansecan support the second chip 40. Thus, the first bonding wire 38 of thefirst chip 34 can support the second chip 40 stacked thereon in a highlystable manner.

The second chip 40 has a second metal bump 43 formed on a secondelectrode pad 41 similar to the first chip 34. The second metal bump 43on the second chip 40 is electrically connected to the wiring pattern 33by a second bonding wire 44 using the bump reverse bonding method.

Accordingly, the semiconductor chip stack structure 30 minimizes thespace S between the first chip 34 and the second chip 40, therebyreducing the total height of semiconductor chip stack.

Although the embodiment described above uses two semiconductor chipsvertically stacked on the substrate 31, it will be appreciated to anordinary skilled person in the art that more chips can be additionallystacked on the substrate 31 in a manner similar to the above-describedembodiment.

Furthermore, although the above-described embodiment uses the bumpreverse bonding method to electrically interconnect the second chip 40and the substrate 31, a conventional wire bonding method may be used forconnecting the second chip to the substrate 31 as shown in FIG. 10.Referring to FIG. 10, the second bonding wire 64 is ball-bonded at oneend to the second electrode pad 61 of the second chip 60 and thenstitch-bonded to the wiring pattern 53 of the substrate 31 at the otherend. For the uppermost semiconductor chip such as the second chip 60 inthis embodiment, it is preferred that the normal wire bonding method beperformed to interconnect the uppermost chip and the substrate 51.

A method for stacking two semiconductor chips in accordance with anembodiment of the present invention is described below with reference toFIGS. 4 through 9.

The semiconductor chip stack method begins with providing a substrate 31as shown in FIG. 4. The substrate 31 includes a substrate body 32 andwiring patterns 33 which are formed on the substrate body 32 anddisposed adjacent to, e.g., surrounding the die-mounting surface 32 a ofthe substrate 31.

Then, the first chip 34 is attached to the die-mounting surface 32 a ofthe substrate 31. The conductive adhesive or a die attach paste 36, suchas Ag-epoxy adhesive, may be used in the attaching step.

Referring to FIG. 5, a first conductive bump 37 is formed on a firstelectrode pad 35 of the first chip 34. The first metal bump 37 may beformed by ball bonding a bonding wire to the first electrode pad 35,thereby forming a wire ball, and then cutting the bonding wire near thetop of the wire ball as illustrated in FIG. 5. Other conductive discreteelements may be used in place of the conductive bump 37.

Referring to FIG. 6, the first chip 34 and the substrate 31 arepreferably interconnected by the bump reverse bonding method. Accordingto the bump reverse bonding method, a ball bonding is performed on thesubstrate 31 and a stitch bonding is performed on the first chip 34.That is, contrary to the normal bonding method, the first bonding wire38 is ball-bonded to the wiring pattern 33 of the substrate 31 and thenstitch-bonded to the first metal bump 37 of the first chip 34. Referencenumeral 38 a refers to a ball-bonded end of the first bonding wire 38and reference numeral 38 b refers to a stitch-bonded end of the firstbonding wire 38. The first bonding wire 38 above the first chip 34 issubstantially parallel with the top surface of the first chip 34 becausethe stitch-bonded end is connected to the first metal bump 37 instead ofthe ball-bonded end, which is formed by a wire bonding process thatrequires a certain rising curve. Thus, other bonding methods that do notrequire a certain rising curve can be used in the present invention.

Referring to FIG. 7, an insulating adhesive 39 is applied on the firstchip 34, specifically, within a portion surrounded by the firstelectrode pads 35 of the first chip 34. The thickness of the insulatingadhesive 39 should be greater than the highest point of the firstbonding wire 38. The insulating adhesive 39 may be epoxy or siliconeinsulating adhesive having a predetermined viscosity.

Referring to FIG. 8, the second chip 40 is stacked over the first chip34 with the insulating adhesive 39. The second chip 40 is placed on andpresses the insulating adhesive 39 with the weight thereof. Theinsulating adhesive 39 having a predetermined viscosity spreads andconsequently seals the space between the first chip 34 and the secondchip 40 hermetically. If the second chip 40 is stacked on the first chip34 without any interposer, the bottom surface of the second chip 40 maymechanically contact the first bonding wire 38 of the first chip 34. Theinsulating adhesive layer 42 is therefore formed on the bottom surfaceof the second chip 40 to prevent the mechanical contact. The insulatingadhesive layer 42 of the second chip 40 is therefore in contact with thefirst bonding wire 38.

The second chip 40 having the insulating adhesive layer 42 may be formedusing conventional techniques. For example, such a chip 40 may beobtained from an ultraviolet (UV) tape used as a dicing tape during awafer sawing process. The UV tape adheres to the bottom surface of thewafer and secures individual chips in the wafer after sawing. Byapplying UV rays to the UV tape, an insulating adhesive layer 42 in theUV tape is detached from the UV tape. Therefore, the insulating adhesivelayer 42 remains adhering to the bottom surface of the chip 20 while thechip 20 is separated from the wafer.

Referring to FIG. 9, the second chip 40 and the substrate 31 areelectrically interconnected through the second bonding wire 44, or othersuitable interconnection means. Like the first bonding wire 38, theinterconnection by the second bonding wire 44 preferably uses the bumpreverse bonding method. Before the interconnection, the second metalbump 43 is formed on the second electrode pad 41 of the second chip 40.

According to another embodiment of the present invention, more chips maybe additionally stacked on the second chip 40 using the techniquesdescribed above.

A package assembly process following the semiconductor chip stackprocess may be identical to a conventional package assembly process.

Although the preferred embodiments of the present invention have beendescribed in detail hereinabove, it should be understood that manyvariations and/or modifications of the basic inventive concepts hereintaught, which may appear to those skilled in the art, will still fallwithin the spirit and scope of the present invention as defined in theappended claims.

1. A method for manufacturing a semiconductor chip stack, the methodcomprising: (a) providing a substrate including a die-mounting surfaceand wiring patterns; (b) attaching a first chip to the die-mountingsurface of the substrate; (c) forming first conductive bumps on firstelectrode pads of the first chip; (d) electrically interconnecting thesubstrate and the first chip through first bonding wires, whereinexpanses of the first bonding wires are substantially parallel with thetop surface of the first chip; (e) stacking a second chip over the firstchip using the expanse; and (f) electrically interconnecting secondelectrode pads of the second chip and the wiring patterns of thesubstrate.
 2. The method of claim 1, wherein one end of each firstbonding wire is ball-bonded to the wiring pattern of the substrate andthe other end of each first bonding wire is stitch-bonded to the firstmetal bump of the first chip.
 3. The method of claim 1, wherein thesecond chip has an insulating adhesive layer on a bottom surfacethereof.
 4. The method of claim 3, wherein the insulating adhesive layeris in contact with the first bonding wire.
 5. The method of claim 1,further comprising applying an insulating adhesive on a top surface ofthe first chip before stacking the second chip over the first chip. 6.The method of claim 5, wherein the insulating adhesive is applied on thetop surface between the first electrode pads of the first chip.
 7. Themethod of claim 5, wherein the insulating adhesive is applied higherthan the highest point of the first bonding wire.
 8. The method of claim1, wherein the substrate is selected from the group consisting of a leadframe, a printed circuit board, a tape wiring substrate and a ceramicsubstrate.
 9. The method of claim 1, wherein the first electrode padsare arranged along a periphery of the top surface of the first chip. 10.The method of claim 1, wherein the second chip is electrically connectedto the substrate through second bonding wires.
 11. The method of claim10, wherein the step (f) includes forming second conductive bumps on thesecond electrode pads of the second chip, wherein the second bondingwire is ball-bonded to the wiring pattern of the substrate at one endand is stitch-bonded to the second metal bump of the second chip at theother end.